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april 2011 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 FAN6920MR ? integrated critical-mode pfc a nd quasi-resonant current-mode pwm controller FAN6920MR integrated critical-mode pfc and quasi-resonant current-mode pwm controller features ? integrated pfc and flyback controller ? critical-mode pfc controller ? zero-current detection for pfc stage ? quasi-resonant operation for pwm stage ? internal minimum 5s t off for qr pwm stage ? internal 5ms soft-start for pwm ? brownout protection ? high / low line over-power compensation ? auto-recovery over-current protection ? auto-recovery open-loop protection ? externally auto-recovery triggering (rt pin) ? adjustable over-temperature protection ? vdd pin and output voltage ovp (auto-recovery) ? internal over-temperature shutdown (140c) applications ? ac/dc nb adapters ? open-frame smps ? battery charger description the highly integrated FAN6920MR combines power factor correction (pfc) cont roller and quasi-resonant pwm controller. integratio n provides cost-effective design and reduces external components. for pfc, FAN6920MR uses a controlled on-time technique to provide a regulated dc output voltage and to perform natural power-fac tor correction. with an innovative thd optimizer, FAN6920MR can reduce input current distortion at zero-crossing duration to improve thd performance. for pwm, FAN6920MR provides several functions to enhance the power system performance: valley detection, green-mode operation, and high / low line over-power compensation. pr otection functions include secondary-side open-loop and over-current with auto- recovery protection; external auto-recovery triggering; adjustable over-temperature pr otection by rt pin; and external ntc resistor, internal over-temperature shutdown, v dd pin ovp, and det pin over-voltage for output ovp, and brown-in / out for ac input voltage uvp. the FAN6920MR controller is available in a 16-pin small-outline package (sop). ordering information part number olp mode operating temperature range package packing method FAN6920MRmy recovery -40c to +105c 16-pin small outline package (sop) tape & reel
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 2 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller application diagram figure 1. typical application circuit
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 3 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller internal block diagram cspwm 2 16 7 3 4 11 5 10 9 12 13 1 8 6 14 0.7v 0.7v 2.5v inv 2.3v comp 0.45v cspfc blanking circuit 0.82v sawtooth generator t on-max thd optimizer multi-vector amp. zcd opfc drv drv gnd 10v i zcd 2.1v/1.75v inhibit timer pfc zero-current detector vdd two-step uvlo 12v/7v/5v internal bias auto-recovery ovp uvp disable function 0.2v restarter pfc current limit 15.5v auto- recovery 17.5v opwm det fb rt vin hv range i hv debounce 2.4v/2.25v pfc range control 1v/1.2v auto-recovery 2.75v 2.65v 2.75v range 2.9v range 4.2v 2r r debounce time 100a soft-start 5ms pwm current limit i det internal otp auto-recovery 100s 10ms 0.8v 0.5v i rt prog. otp / externally triggering blanking circuit i det 5v auto-recovery (rt pin) prog. otp brownout q q set clr s r q q set clr s r v b &clamp v comp to 1.6v fb olp timer 50ms vb over-power compensation pfc burst mode v ctrl-pfc starter 2.25ms 28s 15 nc 2.3v/0.8v v inv 27.5v ovp 1.2v v inv startup v in i comp-burst s/h det ovp 2.5v t off blanking (2.5s) v det auto-recovery valley detector (30a) i det 1st valley t off-min +9s pwm-on/off debounce 100ms brownout comparator comp-h v comp-h auto- recovery protection brownout protection (rt pin) externally triggering det pin ovp vdd pin ovp internal otp debounce debounce 70s 5v pfc burst mode v comp-h v inv comp-l comp-h comp-l v comp-l t off-min (5s/20.5s/2.25ms) auto-recovery figure 2. functional block diagram
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 4 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller marking information 1 16 zxytt fan6920fo tpm figure 3. marking diagram pin configuration gnd det fb rt vin zcd n.c. hv opwm vdd opfc cspwm cspfc inv comp range 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 figure 4. pin configuration pin definitions pin # name description 1 range the range pin?s impedance changes according to vin pin voltage level. when the input voltage detected by the vin pin is higher than a threshold voltage, it sets to low impedance; whereas it sets to high impedance if input voltage is at a high level. 2 comp output pin of the error amplifier. it is a tr ansconductance-type error amplifier for pfc output voltage feedback. proprietary mult i-vector current is built-in to this amplifier; therefore, the compensation for pfc voltage feedback loop allows a simple compensation circuit between this pin and gnd. 3 inv inverting input of the error amplifier. this pin is used to receive pfc voltage level by a voltage divider and provides pfc output over- and under-vol tage protections. this pin also controls the pwm startup. once the FAN6920MR is turned on and v inv exceeds in 2.3v, pwm starts. 4 cspfc input to the pfc over-current protection comparat or that provides cycle-by-cycle current limiting protection. when the sensed voltage across the pfc current-sensing resistor reaches the internal threshold (0.82v typical), the pfc switch is turned off to acti vate cycle-by-cycle current limiting. 5 cspwm input to the comparator of the pwm over-cu rrent protection and performs pwm current-mode control with fb pin voltage. a resistor is used to sense the switching current of the pwm switch and the sensing voltage is applied to the cspwm pi n for the cycle-by-cycle current limit, current- mode control, and high / low line over-power com pensation according to det pin source current during pwm t on time. continued on the following page? - fairchild logo z - plant code x - year code y - week code tt - die run code f - frequency (m = low, h = high level) o - olp mode (l = latch, r = recovery) t - package type (m = sop) p - y = green compound m - manufacturing flow code
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 5 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller pin definitions (continued) pin # name description 6 opfc totem-pole driver output to drive the external power mosfet. the clamped gate output voltage is 15.5v. 7 vdd power supply. the threshold voltages for star tup and turn-off are 12v and 7v, respectively. the startup current is less than 30a and the o perating current is lower than 10ma. 8 opwm totem-pole output generates the pwm signal to dr ive the external power mosfet. the clamped gate output voltage is 17.5v. 9 gnd the power ground and signal ground. 10 det this pin is connected to an auxiliary winding of the pwm transformer through a resistor divider for the following purposes: ? producing an offset voltage to compensate the th reshold voltage of pwm current limit for over- power compensation. the offset is generated in accordance with the input voltage when the pwm switch is on. ? detecting the valley voltage signal of drain volt age of the pwm switch to achieve the valley voltage switching and minimize t he switching loss on the pwm switch. ? providing output over-voltage protection. a volt age comparator is built in to the det pin. the det pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. this flat voltage is reflected to the secondary wind ing during pwm inductor discharge time. if output over voltage and this flat voltage are higher than 2.5v, the controller stops all pfc and pwm switching operation. the prot ection mode is auto-recovery. 11 fb feedback voltage pin used to receive the output voltage level signal to determine pwm gate duty for regulating output voltage. the fb pin voltage can also activate open-loop, overload protection and output-short circuit protection if the fb pin volt age is higher than a threshold of around 4.2v for more than 50ms.the input impedance of this pin is a 5k ? ? ? equivalent resistance. a 1/3 attenuator is connected between the fb pin and the input of the cspwm/fb comparator. 12 rt adjustable over-temperature prot ection and external protection triggering. a constant current flows out from the rt pin. when rt pin voltage is lower than 0.8v (typical), protection is activated and stops pfc and pwm switching operat ion. this protection is auto-recovery. 13 vin line-voltage detection for brownin / out protecti ons. this pin can receive the ac input voltage level through a voltage divider. the voltage level of the vin pin is not only used to control range pin?s status, but it can also perform brow nin / out protection for ac input voltage uvp. 14 zcd zero-current detection for the pfc stage. this pi n is connected to an auxiliary winding coupled to pfc inductor winding to detect the zcd voltage si gnal once the pfc inductor current discharges to zero. when the zcd voltage signal is detect ed, the controller starts a new pfc switching cycle. when the zcd pin voltage is pulled to under 0.2v (typical), it disables the pfc stage and the controller stops pfc switching. this can be re alized with an external circuit if disabling the pfc stage is desired. 15 nc no connection 16 hv high-voltage startup pin is connected to t he ac line voltage through a resistor (100k ? ? ? typical) for providing a high charging current to v dd capacitor.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 6 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage 30 v v hv hv 500 v v h opfc, opwm -0.3 25.0 v v l others (inv, comp, cspfc, det, fb, cspwm, rt) -0.3 7.0 v v zcd input voltage to zcd pin -0.3 12.0 v p d power dissipation 800 mw ja thermal resistance (junction-to-air) 104 c/w jc thermal resistance (junction-to-case) 41 c/w t j operating junction temperature -40 +150 c t stg storage temperature range -55 +150 c t l lead temperature (soldering, 10 seconds) +260 c esd human body model, jesd22-a114 (all pins except hv pin) (3) 4500 v charged device model, jesd22-c101 (all pins except hv pin) (3) 1250 notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 2. all voltage values, except differential voltag es, are given with respect to the gnd pin. 3. all pins including hv pin: cdm=750v, hbm 1000v. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit t a operating ambient tem perature -40 +105 c
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 7 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller electrical characteristics v dd =15v, t a =-40c~105 c (t a =t j ), unless otherwise specified. symbol parameter conditions min. typ. max. units v dd section v op continuously operating voltage 25 v v dd-on turn-on threshold voltage 10.5 12.0 13.5 v v dd-pwm-off pwm off threshold voltage 6 7 8 v v dd-off turn-off threshold voltage 4 5 6 v i dd-st startup current v dd = v dd-on - 0.16v, gate open 20 30 a i dd-op operating current v dd = 15v, opfc, opwm = 100khz, c l-pfc , c l-pwm = 2nf 10 ma i dd-green green-mode operating supply current (average) v dd = 15v, opwm = 450hz, c l-pwm = 2nf 5.5 ma i dd-pwm-off operating current at pwm-off phase v dd = v dd-pwm-off - 0.5v 70 120 170 a v dd-ovp v dd over-voltage protection (auto-recovery) 26.5 27.5 28.5 v t vdd-ovp v dd ovp debounce time 100 150 200 s hv startup current source section i hv supply current drawn from hv pin v ac = 90v (v dc = 120v), v dd = 0v 1.3 ma hv = 500v, v dd = v dd-off +1v 1.0 a vin and range section v vin-uvp threshold voltage for ac input under-voltage protection 0.95 1.00 1.05 v v vin-re-uvp under-voltage protection reset voltage v vin-uvp +0.15v v vin-uvp +0.20v v vin-uvp +0.25v v t vin-uvp under-voltage protection debounce time 70 100 130 ms v vin-range-h high v vin threshold for range comparator 2.40 2.45 2.50 v v vin-range-l low v vin threshold for range comparator 2.20 2.25 2.30 v t range range-enable / disable debounce time 60 90 120 ms v range-ol output low voltage of range pin i o = 1ma 0.5 v i range-oh output high leakage current of range pin range = 5v 50 na t on-max-pfc pfc maximum on time r mot = 24k ? 22 25 28 s continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 8 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller electrical characteristics (continued) v dd =15v, t a =-40c ~105c (t a =t j ), unless otherwise specified. symbol parameter conditions min. typ. max. units pfc stage voltage error am plifier section gm transconductance (4) 100 125 150 mho v ref feedback comparator reference voltage 2.465 2.500 2.535 v v inv-h clamp high feedback voltage range = open 2.70 2.75 2.80 v range = ground 2.60 2.65 2.70 v ratio clamp high output voltage ratio (4) v inv-h / v ref , range = open 1.06 1.14 v/v v inv-h / v ref , range = ground 1.04 1.08 v inv-l clamp low feedback voltage 2.25 2.35 2.45 v v inv-ovp over-voltage protection for inv input range = open 2.90 2.95 v range = ground 2.75 2.80 t inv-ovp over-voltage protection debounce time 50 70 90 s v inv-uvp under-voltage protection for inv input 0.35 0.45 0.55 v v inv-pwmon pwm on threshold voltage on inv pin 2.2 2.3 2.4 v v hyst-pwmon hysteresis for pwm on threshold voltage on inv pin v inv- pwmon -1.6 v inv- pwmon -1.5 v inv- pwmon -1.4 v t inv-uvp under-voltage protection debounce time 50 70 90 s v inv-bo pwm and pfc off threshold for brownout protection 1.15 1.20 1.25 v v comp-bo limited voltage on comp pin for brownout protection 1.55 1.60 1.65 v i comp-burst internal bias current for pfc burst mode 120 150 180 a v comp-h comparator output high voltage 4.80 5.20 v comparator output high voltage at pfc burst mode v fb = 1.3v, v vin = 1.2v 2.20 2.30 2.40 v fb = 1.3v, v vin = 1.6v 2.00 2.10 2.20 v fb = 1.3v, v vin = 2v 1.80 1.90 2.00 v comp-l comparator output low voltage at pfc burst mode range = open, v fb = 1.3v 0.9 1.0 1.1 v v oz zero duty cycle voltage on comp pin 1.10 1.25 1.40 v i comp comparator output source current v inv = 2.3v, v comp = 1.5v 15 30 45 a v inv = 1.5v 0.50 0.75 1.00 ma comparator output sink current range = open, v inv = 2.75v, v comp = 5v 20 30 40 a range = ground, v inv = 2.65v, v comp = 5v 20 30 40 continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 9 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller electrical characteristics (continued) v dd =15v, t a =-40c ~105c (t a =t j ), unless otherwise specified. symbol parameter conditions min. typ. max. units pfc current-sense section v cspfc threshold voltage for peak current cycle-by-cycle limit v comp = 5v 0.77 0.82 0.87 v t pd propagation delay 110 200 ns t bnk leading-edge blanking time 110 180 250 ns a v cspfc compensation ratio for thd 0.90 0.95 1.00 v/v pfc output section v z pfc gate output clamping voltage v dd = 25v 14.0 15.5 17.0 v v ol pfc gate output voltage low v dd = 15v, i o = 100ma 1.5 v v oh pfc gate output voltage high v dd = 15v, i o = 100ma 8 v t r pfc gate output rising time v dd = 12v, c l = 3nf, 20~80% 30 65 100 ns t f pfc gate output falling time v dd = 12v, c l = 3nf, 80~20% 30 50 70 ns pfc zero-current detection section v zcd input threshold voltage rising edge v zcd increasing 1.9 2.1 2.3 v v zcd-hyst threshold voltage hysteresis v zcd decreasing 0.25 0.35 0.45 v v zcd-high upper clamp voltage i zcd = 3ma 8 10 v v zcd-low lower clamp voltage 0.35 0.45 0.55 v v zcd-ssc starting source current threshold voltage 0.70 0.90 1.10 v t delay maximum delay from zcd to output turn-on v comp = 5v, f s = 60khz 100 200 ns t restart-pfc restart time 300 500 700 s t inhib inhibit time (maximum switching frequency limit) v comp = 5v 1.5 2.5 3.5 s v zcd-dis pfc enable / disable function threshold voltage 0.15 0.20 0.25 v t zcd-dis pfc enable / disable function debounce time v zcd = 100mv 100 150 200 s continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 10 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller electrical characteristics (continued) v dd =15v, t a =-40c ~105c (t a =t j ), unless otherwise specified. symbol parameter conditions min. typ. max. units pwm stage feedback input section a v input-voltage to current sense attenuation (4) a v = ? v cs / ? v fb , 0 < v cs < 0.9 1/2.75 1/3.00 1/3.25 v/v z fb input impedance (4) v fb > v g 3 5 7 k ? i oz bias current v fb = v oz 1.2 2.0 ma v oz zero duty cycle input voltage 0.7 0.9 1.1 v v fb-olp open-loop protection threshold voltage 3.9 4.2 4.5 v t fb-olp the debounce time for open- loop protection 40 50 60 ms t fb-ss internal soft-start time (4) v fb = 0v~3.6v 4 5 6 ms det pin ovp and valley detection section v det-ovp comparator reference voltage 2.45 2.50 2.55 v av open-loop gain (4) 60 db bw gain bandwidth (4) 1 mhz t det-ovp output ovp (auto-recovery) debounce time 100 150 200 s i det-source maximum source current v det = 0v 1 ma v det-low lower clamp voltage i det = 1ma 0.15 0.25 0.35 v t valley-delay delay time from valley signal detected to output turn-on (4) 150 200 250 ns t off-bnk leading-edge blanking time for det-ovp (2.5v) and valley signal when pwm mos turns off (4) 2.5 s t time-out time-out after t off-min (4) 8 9 10 s pwm oscillator section t on-max-pwm maximum on-time 38 45 52 s t off-min minimum off-time v fb R v n , t a = 25c 5 s v fb = v g 20.5 v n beginning of green-on mode at fb voltage level 1.95 2.10 2.25 v v g beginning of green-off mode at fb voltage level 1.00 1.15 1.30 v v g hysteresis for beginning of green-off mode at fb voltage level (4) 0.1 v continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 11 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller electrical characteristics (continued) v dd =15v, t a =-40 c~105c (t a =t j ), unless otherwise specified. symbol parameter conditions min. typ. max. units v ctrl-pfc-bm threshold voltage on fb pin for pfc burst mode range pin internally open 1.65 1.70 1.75 v range pin internally ground 1.60 1.65 1.70 v ctrl-pfc-on threshold voltage on fb pin for pfc normal operating 1.75 1.80 1.85 v t pfc-bm debounce time for pfc burst mode pfc normal operating ? burst mode 100 ms t pfc-on debounce time for pfc recovery to normal operating pfc burst mode ? normal operating 200 s t starter-pwm start timer (time-out timer) v fb v g , t a = 25c 1.85 2.25 2.65 ms v fb v fb-olp , t a = 25 c 22 28 34 s pwm output section v clamp pwm gate output clamping voltage v dd = 25v 16.0 17.5 19.0 v v ol pwm gate output voltage low v dd = 15v, i o = 100ma 1.5 v v oh pwm gate output voltage high v dd = 15v, i o = 100ma 8 v t r pwm gate output rising time c l = 3nf, v dd = 12v, 20~80% 80 110 ns t f pwm gate output falling time c l = 3nf, v dd = 12v, 20~80% 40 70 ns current sense section t pd delay to output 150 200 ns v limit limit voltage on cspwm pin for over-power compensation i det 75a, t a = 25c 0.81 0.84 0.87 v i det = 185a, t a = 25c 0.69 0.72 0.75 i det = 350a, t a = 25c 0.55 0.58 0.61 i det = 550a, t a = 25c 0.37 0.40 0.43 v slope slope compensation (4) t on = 45s, range = open 0.25 0.30 0.35 v t on = 0s 0.05 0.10 0.15 t on-bnk leading-edge blanking time 300 ns v cs-floating cspwm pin floating v cspwm clamped high voltage cspwm pin floating 4.5 5.0 v t cs-h delay time, cs pin floating cspwm pin floating 150 s continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 12 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller electrical characteristics (continued) v dd =15v, t a =-40c~105 c (t a =t j ), unless otherwise specified. symbol parameter conditions min. typ. max. units rt pin over-temperature protection section t otp internal threshold temperature for otp (4) 125 140 155 c t otp-hyst hysteresis temperature for internal otp (4) 30 c i rt internal source current of rt pin 90 100 110 a v rt-ar protection triggering volt age 0.75 0.80 0.85 v v rt-otp-level threshold voltage for two-level debounce time 0.45 0.50 0.55 v t rt-otp-h debounce time for otp 10 ms t rt-otp-l debounce time for externally triggering v rt < v rt-otp-level 70 110 150 s note: 4. guaranteed by design.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 13 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller typical performance characteristics these characteristic graphs are normalized at t a =25c. 10 10.5 11 11.5 12 12.5 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v dd-on (v) 7.45 7.5 7.55 7.6 7.65 7.7 7.75 7.8 7.85 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v dd-pwm-off (v) figure 5. turn-on threshold voltag e figure 6. pwm-off threshold voltage 0 1 2 3 4 5 6 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v dd-off (v) 27.0 27.5 28.0 28.5 29.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v dd-ovp (v) figure 7. turn-off threshold voltage figure 8. v dd ove r - v oltage protection threshold 6.0 8.0 10.0 12.0 14.0 16.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) i dd-st ( ? a) 4.0 5.0 6.0 7.0 8.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) i dd-op (ma) figure 9. startup current figure 10. operating current 2.40 2.45 2.50 2.55 2.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v ref (v) 14.0 14.5 15.0 15.5 16.0 16.5 17.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v z (v) figure 11. pfc output feedback reference voltage figure 12. pfc gate output clamping voltage
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 14 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller typical performance characteristics (continued) these characteristic graphs are normalized at t a =25c. 22.0 23.0 24.0 25.0 26.0 27.0 28.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) t on-max-pfc ( ? sec) 0.75 0.80 0.85 0.90 0.95 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v cspfc (v) figure 13. pfc maximum on-time figure 14. pfc peak current limit voltage 16.0 16.5 17.0 17.5 18.0 18.5 19.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v clamp (v) 38 39 40 41 42 43 44 45 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) t on-max-pwm (s) figure 15. pwm gate output clamping voltage figure 16. pwm maximum on-time 1.9 2.0 2.1 2.2 2.3 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v n (v) 1.0 1.1 1.2 1.3 1.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v g (v) figure 17. beginning of green-on mode at v fb figure 18. beginning of green-off mode at v fb 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) t off,min (s) 18 18.5 19 19.5 20 20.5 21 21.5 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) t off,min (s) figure 19. pwm minimum of f -time for v fb > v n figure 20. pwm minimum of f -time for v fb =v g
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 15 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller typical performance characteristics (continued) these characteristic graphs are normalized at t a =25c. 0.27 0.275 0.28 0.285 0.29 0.295 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v det-low (v) 2.40 2.45 2.50 2.55 2.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v det-ovp (v) figure 21. lower clamp voltage of det pin figure 22. reference voltage for output over-voltage protection of det pin 90 95 100 105 110 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) i rt ( ? a) 0.70 0.75 0.80 0.85 0.90 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature( o c) v rt-latch (v) figure 23. internal source current of rt pin figure 24. ove r -temperature protection threshold voltage of rt pin
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 16 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller functional description pfc stage multi-vector error amplifier and thd optimizer for better dynamic performance, faster transient response, and precise clamping on the pfc output, FAN6920MR uses a transc onductance type amplifier with proprietary innovative mu lti-vector error amplifier ( us patent 6,900,623 ). the schematic diagram of this amplifier is shown in figure 25. the pfc output voltage is detected from the inv pin by an external resistor divider circuit that consists of r 1 and r 2 . when pfc output variation voltage reac hes 6% over or under the reference voltage of 2.5v, the multi-vector error amplifier adjusts its output si nk or source current to increase the loop response to simplify the compensated circuit. figure 25. multi-vector error amplifier the feedback voltage signal on the inv pin is compared with reference voltage 2.5v, which makes the error amplifier source or sink cu rrent to charge or discharge its output capacitor c comp . the comp voltage is compared with the internally generated sawtooth waveform to determine the on-time of pfc gate. normally, with lower feedback loop bandwidth, the variation of the pfc gate on- time should be very small and almost constant within one input ac cycle. however, the power factor co rrection circuit operating at light-load condition has a defect, zero crossing distortion; which distorts input current and makes the system?s total harmonic distortion (thd) worse. to improve the result of thd at light-load condition, especially at high input voltage, an innovative thd optimizer ( us patent 7,116,090 ) is inserted by sampling the voltage across the curr ent-sense resistor. this sampling voltage on current-sense resistor is added into the sawtooth waveform to modulate the on-time of pfc gate, so it is not constant on-time within a half ac cycle. the method of operation block between thd optimizer and pwm is shown in figure 26. after thd optimizer processes, around the valley of ac input voltage, the compensated on-time becomes wider than the original. the pfc on-time, which is around the peak voltage, is narrowed by the thd optimizer. the timing sequences of the pfc mos and the shape of the inductor current are shown in figure 27. figure 28 shows the difference between calculated fixed on-time mechanism and fixed on-time with thd optimizer during a half ac cycle. 4 3 ? + + 2.5v inv pfc v o error amplifier v comp rs filp-flop cspfc pfc mos r s FAN6920MR sawtooth generator thd optimizer r 1 r 2 figure 26. multi-vector error amplifier with thd optimizer figure 27. operation waveforms of fixed on-time with and without thd optimizer current (a) figure 28. calculated waveforms of fixed on-time with and without thd optimizer during a half ac cycle
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 17 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller range pin a built-in low-voltage mosfet can be turned on or off according to v vin voltage level and pfc status. the drain pin of this internal mosfet is connected to the range pin. figure 29 shows the status curve of v vin voltage level and range impedance (open or ground). figure 29. hysteresis behavior between range pin and vin pin voltage zero-current detection (zcd pin) figure 30 shows the internal block of zero-current detection. the detection function is performed by sensing the information on an auxiliary winding of the pfc inductor. referring to figure 31, when pfc mos is off, the stored energy of th e pfc inductor starts to release to the output load. then the drain voltage of pfc mos starts to decrease since the pfc inductor resonates with parasitic capacitance. once the zcd pin voltage is lower than the triggering voltage (1.75v typical), the pfc gate signal is sent again to start a new switching cycle. if pfc operation needs to be shut down due to abnormal condition, pull the zcd pin low, voltage under 0.2v (typical), to acti vate the pfc disable function to stop pfc switching operation. for preventing excessive high switching frequency at light load, a built-in inhibit timer is used to limit the minimum t off time. even if the zcd signal has been detected, the pfc gate signal is not sent during the inhibit time (2.5s typical). figure 30. internal block of the zero-current detection v zcd pfc gate v in,max pfcvo v ds 10v 2.1v 1.75v inhibit time t t t figure 31. operation waveforms of pfc zero-current detection protection for pfc stage pfc output voltage uvp and ovp (inv pin) FAN6920MR provides several kinds of protection for pfc stage. pfc output over- and under-voltage are essential for pfc stage. both are detected and determined by inv pin voltage, as shown in figure 32. when inv pin voltage is over 2.75v or under 0.45v, due to overshoot or abnormal conditions, and lasts for a de- bounce time around 70s; the ovp or uvp circuit is activated to stop pfc swit ching operation immediately. the inv pin is not only used to receive and regulate pfc output voltage; it c an also perform pfc output ovp/ uvp protection. for failure-mode test, this pin can shut down pfc switching if pin floating occurs . figure 32. internal block of pfc over- and under-voltage protection
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 18 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller pfc peak current limiting (cspfc pin) during pfc stage switching operation, the pfc switch current is detected by the current-sense resistor on the cspfc pin and the detected volt age on this resistor is delivered to the input terminal of a comparator and compared with a threshold voltage 0.82v (typical). once the cspfc pin voltage is higher than the threshold voltage, the pfc gate is turned off immediately. the pfc peak switching current is adjustable by the current-sense resistor. figure 33 shows the measured waveform of pfc gate and cspfc pin voltage. figure 33. cycle-by-cycle current limiting brownout / in protection (vin pin) with ac voltage detection, FAN6920MR can perform brownout / in protection (ac voltage uvp). figure 34 shows the key operation waveforms of brownout / in protection. both use the vin pin to detect ac input voltage level and the vin pin is connected to ac input by a resistor divider (refer to figure 1) ; therefore, the v vin voltage is proportional to the ac input voltage. when the ac voltage drops and v vin voltage is lower than 1v for 100ms, the uvp pr otection is activated and the comp pin voltage is clamped to around 1.6v. because pfc gate duty is determined by comparing the sawtooth waveform and comp pin voltage, lower comp voltage results in nar row pfc on-time, so that the energy converged is limited and the pfc output voltage decreases. when inv pin is lower than 1.2v, FAN6920MR stops all pfc and pwm switching operation immediately until v dd voltage drops to turn-off voltage then rises to turn-on voltage again (uvlo). when the brownout protection is activated, all switching operation is turned off and, v dd voltage enters hiccup mode up and down continuously. until v vin voltage is higher than 1.3v (typical) and v dd reaches turn-on voltage again, the pwm and pfc gate is sent. the measured waveforms of brownout / in protection are shown in figure 35. figure 34. operation waveforms of brownout / in protection figure 35. measured waveform of brownout / in protection (adapter application) opfc opwm ac input v dd v dd hiccup mode brownout brown-in opfc cspfc pfc mos current limit 0.82v
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 19 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller pfc burst mode to minimize the power dissipation at light-load condition, the FAN6920MR pfc control enters burst- mode operation. as the load decreases, the pwm feedback voltage (v fb ) decreases. when v fb < v ctrl- pfc-bm for 100ms, the device ent ers pfc burst mode, the v comp pulls high to v comp-h , and pfc output voltage increases. when the pfc feedback voltage on inv pin (v inv ) triggers the ovp threshold voltage (v inv-ovp ), v comp pulls low to v comp-l , the opfc pin switching stops and the pfc output volt ages start to drop. once the v inv drops below the feedback comparator reference voltage (v ref ), v comp pulls high to v comp-h and opfc starts switching again. bu rst-mode operation alternately enables and disables switch ing of the power mosfet to reduce the switching loss at light-load condition. figure 36. pfc burst mode behavior the v comp-h is adjusted by the volt age of the vin pin, as shown in figure 1. since the vin pin is connected to rectified ac input line voltage through the resistive divider, a higher line volta ge generates a higher vin pin voltage. the v comp-h decreases as vin pin voltage increases, making the pfc c hoke current be limited at a higher input voltage to reduce acoustic noise. if the v comp-h is below the pfc v oz , the pfc automatically shuts down at light load with high line voltage input condition. figure 37. v comp-h voltage vs. v vin voltage characteristic curve pwm stage hv startup and operating current (hv pin) the hv pin is connected to the ac line through a resistor (refer to figure 1) . with a built-in high-voltage startup circuit, when ac voltage is applied to the power system, FAN6920MR provides a high current to charge the external v dd capacitor to speed up controller?s startup time and build up normal rated output voltage within three seconds. to save power consumption, after v dd voltage exceeds turn-on voltage and enters normal operation; this high-voltage st artup circuit is shut down to avoid power loss from startup resistor. figure 1 shows the characteristic curve of v dd voltage and operating current i dd . when v dd voltage is lower than v dd-pwm-off , FAN6920MR stops all switching operation and turns off unnecessary internal circuits to reduce operating current. by doing so, the period from v dd-pwm-off to v dd-off can be extended and the hiccup mode frequency can be decreased to reduce the input power in case of output short circuit. figure 39 shows the typical waveforms of v dd voltage and gate signal with hiccup mode operation. figure 38. v dd vs. i dd-op characteristic curve
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 20 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller v dd-on v dd-pwm-off v dd-off gate i dd-pwm-off i dd-st i dd-op figure 39. typical waveform of v dd voltage and gate signal at hiccup mode operation green-mode operation and pfc-on / off control (fb pin) green mode further reduces power loss in the system (e.g. switching loss). through off-time modulation to regulate switching frequency according to fb pin voltage. when output load ing decreases, fb voltage lowers due to secondary feedback movement and the t off-min is extended. after t off-min (determined by fb voltage), the internal valley-detection circuit is activated to detect the valley on the drain voltage of the pwm switch. when the valley signal is detected, FAN6920MR outputs a pwm gate signal to turn on the switch and begin a new switching cycle. with green mode operation and valley detection, at light-load condition; the power system can perform extended valley switching a dcm operation and can further reduce switching loss for better conversion efficiency. the fb pin voltage versus t off-min time characteristic curve is shown in figure 40. as figure 40 shows, FAN6920MR can narrow down to 2.25ms t off time, which is around 440hz switching frequency. referring to figure 1 and figure 2, fb pin voltage is not only used to receive secondary feedback signal to determine gate on-time, but also determines pfc stage operating mode. figure 40. v fb voltage vs. t off-min time characteristic curve valley detection (det pin) when FAN6920MR operates in green mode, t off-min is determined by the green-mode circuit according to fb pin voltage level. after t off-min , the internal valley- detection circuit is activated. during t off of the pwm switch, when transformer inductor current discharges to zero, the transformer inductor and parasitic capacitor of pwm switch start to resonate concurrently. when the drain voltage on the pwm switch falls, the voltage across on auxiliary winding v aux also decreases since auxiliary winding is coupled to primary winding. once the v aux voltage resonates and falls to negative, v det voltage is clamped by the det pin (refer to figure 41) and FAN6920MR is forced to flow out a current i det . FAN6920MR reflects and compares this i det current. if this source current rises to a threshold current, pwm gate signal is sent out after a fixed delay time (200ns typical). figure 41. valley detection figure 42. measured waveform of valley detection high / low line over-power compensation (det pin) generally, when the power switch turns off, there is a delay from gate signal falling edge to power switch off. this delay is produced by an internal propagation delay of the controller and the turn-off delay of the pwm switch due to gate resistor and gate-source capacitor c iss . at different ac input voltages, this delay produces different maximum output power with the same pwm current limit level. higher in put voltage generates higher maximum output power because applied voltage on primary winding is higher and causes higher rising slope inductor current. it results in higher peak inductor current at the same delay. furthermore, under the same output wattage, the peak switch ing current at high line is lower than that at low line. therefore, to make the maximum output power close at different input voltages, the controller needs to regulate v limit voltage of the cspwm pin to control the pwm switch current. referring to figure 1, during t on of the pwm switch, the input voltage is applied to primary winding and the voltage across on auxiliary winding v aux is proportional to primary winding voltage. as the input voltage increases, the reflected voltage on auxiliary winding v aux becomes higher as well. FAN6920MR also clamps t off start to detect valley i det flow out from det pin delay time and then trigger gate signal valley switching 0v 0v v det opwm v aux
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 21 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller the det pin voltage and flows out current i det . since the current i det is in accordance with v aux voltage, FAN6920MR depends on this current during t on to regulate the current limit le vel of the pwm switch to perform high / low line over-power compensation. as the input voltage increas es, the reflected voltage on the auxiliary winding v aux becomes higher as well as the current i det and the controller regulates the v limit to a lower level. the r det resistor is connected from auxiliary winding to the det pin. engineers can adjust this r det resistor to get proper v limit voltage to fit power system needs. the characteristic curve of i det current vs. v limit voltage on cspwm pin is shown in figure 44. ?? d et in a p det i vnnr ?? ?? ?? (1) where v in is input voltage; n a is turn number of auxiliary winding; and n p is turn number of primary winding. figure 43. relationship between v aux and v in figure 44. i det current vs. v limit voltage characteristic curve leading-edge blanking (leb) when the pfc or pwm switches are turned on, a voltage spike is induced on the current-sense resistor due to the reciprocal effect by reverse-recovery energy of the output diode and c oss of power mosfet. to prevent this spike, a leading-edge blanking time is built- in and a small rc filter (e.g. 100 ? , 470pf) is recommended between the cspwm pin and gnd. protection for pwm stage vdd pin over-voltage protection (ovp) v dd over-voltage protection prevents device damage once v dd voltage is higher than device stress rating voltage. in the case of v dd ovp, the controller stops all switching operation immediately and enters auto- recovery protection. adjustable over-temperature protection and externally protection triggering (rt pin) figure 45 is a typical application circuit with an internal block of rt pin. as show n, a constant current i rt flows out from the rt pin, so the voltage v rt on the rt pin can be obtained as i rt current multiplied by the resistor, which consists of ntc resistor and r a resistor. if the rt pin voltage is lower than 0.8v and lasts for a debounce time, auto-recovery protection is activated and stops all pfc and pwm switching. rt pin is usually used to achieve over-temperature protection with a ntc resistor and provides external protection triggering for additional protection. engineers can use an external triggering circuit (e.g. transistor) to pull the rt pin low and activate controller auto-recovery protection. generally, the external protection triggering needs to activate rapidly since it is usually used to protect the power system from abnormal conditions. therefore, the protection debounce time of the rt pin is set to around 110s once the rt pin voltage is lower than 0.5v. for over-temperature pr otection, because the temperature does not change immediately; the rt pin voltage is reduced slowly as well. the debounce time for adjustable otp should not need a fast reaction. to prevent improper protection triggering on the rt pin due to exacting test condition (e.g. lightning test); when the rt pin triggering voltage is higher than 0.5v, the protection debounce time is set to around 10ms. to avoid improper triggering on the rt pin, add a small value capacitor (e.g. 1000pf) paralleled with ntc and the r a resistor. figure 45. adjustable over-temperature protection v det opwm v aux
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 22 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller output over-voltage protection (det pin) referring to figure 1, during the discharge time of pwm transformer inductor; the voltage across on auxiliary winding is reflected from secondary winding and therefore the flat voltage on the det pin is proportional to the output voltage. FAN6920MR can sample this flat voltage level after a t off blanking time to perform output over-voltage protection. this t off blanking time is used to ignore the voltage ringin g from leakage inductance of pwm transformer. the sampling flat voltage level is compared with internal threshold voltage 2.5v and, once the protection is activat ed, FAN6920MR enters auto- recovery protection. the controller can protect rapidly by this kind of cycle- by-cycle sampling method in the case of output over voltage. the protection volt age level can be determined by the ratio of external resistor divider r a and r det . the flat voltage on det pin can be expressed by the following equation: ?? a det a s o d et a r vnnv r r ??? ? (2) a det a s a o r r r n n v ? ? ? v det pwm gate v aux p a o n n v pfc ? _ 0.3 v t off blanking sampling here s a o n n v ? t t t figure 46. operation waveform of output over-voltage detection open-loop, short-circuit, and overload protection (fb pin) figure 47. fb pin open-loop, short circuit, and overload protection referring to figure 47; outside of FAN6920MR, the fb pin is connected to the collec tor of transistor of an opto- coupler. inside, the fb pin is connected to an internal voltage bias through a resistor of around 5k ? . as the output loading is increa sed, the output voltage is decreased and the sink current of the transistor of the opto-coupler on primary si de is reduced. the fb pin voltage is increased by internal voltage bias. in the case of an open loop, output short-circuit, or overload condition; this sink current is further reduced and the fb pin voltage is pulled high by internal bias voltage. when the fb pin voltage is higher than 4.2v for 50ms, the fb pin protection is activated . under-voltage lockout (uvlo, vdd pin) referring to figure 1 and figure 39, the turn-on and turn-off v dd threshold voltages are fixed at 18v and 10v, respectively. during startup, the hold-up capacitor (v dd capacitor) is charged by hv startup current until v dd voltage reaches the turn-on voltage. before the output voltage rises to rated voltage and delivers energy to the v dd capacitor from auxiliary winding, this hold-up capacitor must sustain the v dd voltage energy for operation. when v dd voltage reaches turn-on voltage, FAN6920MR starts all switching operation if no protection is triggered before v dd voltage drops to turn- off voltage v dd-pwm-off .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 23 FAN6920MR ? integrated critical-mode pfc and quasi-resonant current-mode flyback pwm controller physical dimensions figure 48. 16-pin small outline package (soic) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ,
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN6920MR ? rev. 1.0.3 24 FAN6920MR ? integrated critical mode pfc a nd quasi-resonant current mode pwm controller

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